Abstract
The paper presents a new word-level systolic array with no broadcasting for implementation of 2-D FIR digital filters. The architecture possesses the desirable features of regularity, modularity, and concurrency for VLSI implementation. As compared to existing related systolic systems with broadcasting, it achieves improved throughput performance with a little increase in the latency and the number of latches. Also, the proposed array has an important feature that the filter coefficients can easily be updated without interrupting the system operations. This makes it attractive for use in applications such as adaptive image processing and image template matching