Abstract
Logic diagnosis is an important task for companies that design, test, and manufacture integrated circuit (ICs). It provides guidance for subsequent failure analysis for design debugging and yield ramp-up. This chapter reviews the diagnosis techniques for combinational logic, scan chains, and logic built-in self-test (BIST), focusing on diagnosis technique for scan chain problems. As for diagnosis in a scan-based logic BIST environment, hardware support is often required to achieve satisfactory results. Moreover, the two most commonly used paradigms-namely, cause-effect analysis and effect-cause analysis-along with their variants are addressed in the chapter. The chapter then describes three different methods for diagnosing faults within the scan chains, including hardware-assisted, modified inject-and-evaluate, and signal-profiling-based methods. Finally, the chapter deals with the challenges of diagnosis in a logic BIST environment. © 2006 Elsevier Inc. All rights reserved.