Abstract
λ-geometry routing provides more available routing directions on different metal layers for chip interconnection to reduce wirelength. However, it can lead to a significant increase in via cost. In this paper, we consider λ-geometry zero-skew clock tree construction with wirelength and via minimization. Our λ-geometry clock router achieves, on average, a 7.57% wirelength reduction in the Y-architecture and 9:68% in the X-architecture when compared with results in the Manhattan, architecture. In addition, we also propose a dynamic programming approach to determine the one-bend routes of the clock edges to optimize the total node via cost of the whole clock tree. Our via minimization algorithm can reduce the total via cost by an average of 1.7% in the Y-architecture and 37% in the X architecture. © 2007 IEEE.