Abstract
Resistive RAM (ReRAM) is a promising nonvolatile memory with low write energy, logic-process compatibility, and compact cell area. The 1T1R ReRAM [1-3] fits embedded applications requiring fast read (RD) access time (T <sub>AC</sub> ) and low RD-V <sub>DDMIN</sub> , particularly for devices powered by batteries or energy harvesters. The cross-point ReRAM [4-6] is meant for high capacities with high RD-V <sub>DDMIN</sub> and slow T <sub>AC</sub> . As devices shrink, ReRAMs have higher cell resistance (R) and greater variations in write time and R, which reduces the R-ratio (R <sub>H</sub> /R <sub>L</sub> ) between the high-R state (HRS, R <sub>H</sub> ) and low-R state (LRS, R <sub>L</sub> ). ReRAM also have a high R <sub>L</sub> , which enables a larger voltage drop across ReRAM to reduce write voltage and cell-switch (CS) size. Thus, ReRAM macro designs suffer: (1) small sensing margin (SM), limited RD-V <sub>DDMIN</sub> , and slow T <sub>AC</sub> due to high-R <sub>L</sub> and small R-ratio; (2) increase in energy due to large set DC-current (I <sub>DC-SET</sub> ) resulting from wide set-time (T <sub>SET</sub> ) distribution. This study develops a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to overcome (1), enabling 1.8× greater SM for lower RD-V <sub>DDMIN</sub> and 1.7× faster T <sub>AC</sub> across various V <sub>DD</sub> , compared to conventional differential-input (CD) VSAs. To reduce >99% set energy, we use a 4T self-boost-write-termination (SBWT) scheme to cut off I <sub>DC-SET</sub> of faster-T <sub>SET</sub> devices, with an area penalty below 0.5%. A fabricated 28nm 1Mb ReRAM macro achieves T <sub>AC</sub> = 404ns at V <sub>DD</sub> = 0.27V and confirms the I <sub>DC-SET</sub> cut-off by SBWT. © 2014 IEEE.