1T EUV/DUV Detector in Fully Compatible 16nm FinFET Logic Process

會議論文

1T EUV/DUV Detector in Fully Compatible 16nm FinFET Logic Process

〇Wei-Hwa Lin, Ting-Kai Huang, Yue Der Chih, Yih Wang, Jonathan Chang, King, Ya Chin 和 Chrong-Jung Lin

2024 International Conference on Solid State Devices and Materials (Arcrea HIMEJI, Japan, 01/09/2024–04/09/2024)

DOI: https://doi.org/10.7567/SSDM.2024.A-2-02

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題名: 1T EUV/DUV Detector in Fully Compatible 16nm FinFET Logic Process
創作者：: 〇Wei-Hwa Lin (作者)
Ting-Kai Huang (作者)
Yue Der Chih (作者)
Yih Wang (作者)
Jonathan Chang (作者)
King, Ya Chin
Chrong-Jung Lin - 國立清華大學, 半導體研究學院
會議: 2024 International Conference on Solid State Devices and Materials (Arcrea HIMEJI, Japan, 01/09/2024–04/09/2024)
學術資源類型: 會議論文
語言: 英語