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28nm HKMG 1F-1R2Multilevel Memory for Inference Engine Application
Conference paper

28nm HKMG 1F-1R2Multilevel Memory for Inference Engine Application

Sourav De, Franz Muller, Maximilian Lederer, Yannick Raffel, Tarek Ali, Luca Pirro, Stefan Dunkel, Sven Beyer, Konrad Seidel and Thomas Kampfe
2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
2023
DOI: https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134004

Abstract

Artificial Intelligence Computer Networks and Communications Computer Science Applications Hardware and Architecture Information Systems Electrical and Electronic Engineering
This article reports 28 nm high-k-metal-gate (HKMG) based 3bits/cell memory with one ferroelectric (Fe) field effect transistor (FeFET) and one reconfigurable resistor (R2). R2, connected with the select line (SL) and the drain terminal of the FeFET, can be reconfigured via the SL terminal. R2 can be implemented by using a standard metal-oxide-semiconductor field effect transistor (MOSFET) as voltage controlled resistor or any two terminal programmable resistors. The detailed discussion about R2 is beyond the scope of this paper. The 1F-1R2 cells demonstrate current-based 3bits/cell operation over a 300mm wafer and stable retention characteristics at 85°C for all eight current levels.

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