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3D Stackable Via RRAM Cells by Cu BEOL Process in FinFET CMOS Technologies
Conference paper

3D Stackable Via RRAM Cells by Cu BEOL Process in FinFET CMOS Technologies

Cheng-Jun Lin, Wang-Yi Lee, Chrong-Jung Lin and Ya-Chin King
2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020, pp.31-32
08/2020
DOI: https://doi.org/10.1109/VLSI-TSA48913.2020.9203679

Abstract

FinFET CMOS;Cu BEOL CMOS Artificial Intelligence Hardware and Architecture Electrical and Electronic Engineering Electronic Optical and Magnetic Materials

In this study, a Vertical Via RRAM fully compatible to cutting-edge FinFET CMOS logic process has been demonstrated. These Vertical Via RRAM devices are formed by the stacked nanometer via and metal in the Cu BEOL CMOS logic process. Between the two Cu electrodes, the TaON-based transition metal oxide (TMO) film functions as the resistive switching layer after a reset forming process. This 3D stackable Vertical Via RRAM features low voltage operation, large read window and enables compact cell size. Excellent data retention and immunity to read disturb are demonstrated as well.

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