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3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi
Conference paper

3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi

Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, …
Digest of Technical Papers - Symposium on VLSI Technology
2024
DOI: https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631506

Abstract

3DIC Elevated Epi Laser recrystallization Electrical and Electronic Engineering
The Elevated Epi technique is presented for the fabrication of single-crystal (100) silicon of wafer field size (25mmx33mm) for monolithic three-dimensional integrated circuits (3DICs). Elevated Epi uses a low substrate temperature, pulse laser technique to fabricate single-crystal Si on dielectric. We also demonstrate 3D inverters, with an inter-layer metal M0 positioned between two layers of FinFETs. A hybrid-3D cell library is presented for improving performance, power, and area of 3DICs.

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