81MS/s JPEG 2000 single-chip encoder with rate-distortion optimization

Hung-Chi Fang; Chao-Tsung Huang; Yu-Wei Chang; Tu-Chih Wang; Po-Chih Tseng; Chung-Jr Lian; Liang-Gae Chen

Back

Conference paper

81MS/s JPEG 2000 single-chip encoder with rate-distortion optimization

Hung-Chi Fang, Chao-Tsung Huang, Yu-Wei Chang, Tu-Chih Wang, Po-Chih Tseng, Chung-Jr Lian and Liang-Gae Chen

Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.47, pp.262-263+563

2003

Abstract

An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm ² die using 0.25μm CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The rate-distortion optimized chip encodes tile size of 128×128, code block size of 64×64, and image size up to 32K×32K.

Metrics

1 Record Views

Details

Title: 81MS/s JPEG 2000 single-chip encoder with rate-distortion optimization
Creators - without role: Hung-Chi Fang - National Taiwan University
Chao-Tsung Huang - National Taiwan University
Yu-Wei Chang - National Taiwan University
Tu-Chih Wang - National Taiwan University
Po-Chih Tseng - National Taiwan University
Chung-Jr Lian - National Taiwan University
Liang-Gae Chen - National Taiwan University
Publication Details: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.47, pp.262-263+563
Grant note: IEEE;Solid-State Circuits Council, SSCS;University
Identifiers: 9957773930606774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

81MS/s JPEG 2000 single-chip encoder with rate-distortion optimization

Abstract

Related links

Metrics

Details

National Tsing Hua University Social media