Abstract
This paper proposes a two-step switching SAR ADC architecture that greatly reduces the area and power consumption of the DAC network. The total number of unit capacitors of the proposed approach is only 64C. In addition, to reduce meta-stability at low-supply operation, a supply-boost technique of comparator is also employed. The prototype chip realized an 11-bit SAR ADC in a 0.18μm CMOS technology with an extremely small core area of 0.05mm 2 . With a single 0.6V supply voltage, the prototype consumes 5.02uW at 500kS/s, and achieves an ENOB of 9.45bit and a FoM of 14.34fJ/conversion-step, respectively. © 2012 IEEE.