Abstract
This study presents a joint QR decomposition and lattice reduction processor for 8×8 multiple-input multiple-output (MIMO) systems. The proposed algorithm enhances the BER performance by lattice reduction and reduces the hardware cost by sharing computation units and removing redundant operations. This processor can be reconfigured as three different modes, including joint QR decomposition and lattice reduction, lattice reduction, and QR decomposition. The proposed processor was implemented in TSMC 90nm 1P9M CMOS technology. The maximum throughput is 1.1 M matrix/s for QR decomposition, and 0.5 M matrix/s for the lattice reduction, and 0.33 M matrix/s for the joint QR decomposition and lattice reduction at a power consumption of 31.2 mW. The energy efficiency achieves 0.18nJ/matrix for the 8×8 MIMO preprocessing including both QR decomposition and lattice reduction. © 2013 IEEE.