Abstract
Many low-voltage chips such as sensor networks and biomedical applications need large-capacity low-V DDmin -delay-product embedded ROM for storing fixed programs and data [1]. NOR-ROMs provide low V DD and high speed for small-capacity applications with a short bitline (BL) [2]. However, if read-1 noise can be eliminated, a NAND-ROM is superior [1] for large-capacity storage in stand-by-dominated low-voltage chips because of smaller area, narrower cell-current (I CELL ) distribution, and lower standby current. Static NAND-ROM with short BL [1] achieves small read-1 noise and low V DD with a 33% area penalty. Applying selected precharge [3], driving source-line (SL) [4], or BL-shield [5], [6] schemes to NAND-ROM can eliminate only one of the read-1 noise sources, which are charge sharing, BL leakage, and BL crosstalk. The remaining read-1 noise reduces the sensing margins for reading 1-cells (V SM1 ) and 0-cells (V SM0 ) and limits the V DDmin and speed of NAND-ROMs. This paper presents dynamic split source-lines (DSSL) scheme to eliminate read-1 noise and a data-aware sensing reference (DASR) scheme to expand V SM0 to tolerate larger I CELL variations for large-capacity low-voltage NAND-ROM. These schemes enable large-capacity NAND-ROM to achieve lower V DDmin , higher speed, and lower power consumption with small area overhead. ©2010 IEEE.