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A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS
Conference paper

A 0.3V 0.705fJ/conversion-step 10-bit SAR ADC with shifted monotonie switching scheme in 90nm CMOS

Sung-En Hsieh and Chih-Cheng Hsieh
Proceedings - IEEE International Symposium on Circuits and Systems, Vol.2016-July, p.2899
29/07/2016

Abstract

Internet-of-things applications require high energy-efficient ADC. Several SAR ADCs have been reported [1-2] with comparatively low FoMs by reducing the switching energy of the power hungry capacitor array. This paper proposes a shifted monotonic switching (SMS) scheme to achieve an average switching energy of 63.75CV2 with a reduction of 75%, 72%, and 73% compared to monotonic switching (MS), sub-ranging (SR) procedure [1], and merge and split (MAS) switching [2] procedure, respectively. Proper redundancy design is also employed to tolerate the non-ideal effects including dynamic comparator offset, Vcm variation, and settling error.

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