Abstract
This paper presents a one-bit third-order discrete-time sigma-delta modulator (DT-SDM) using standard CMOS 0.18-μm process. Switched-opamp (SO) technique was utilized to deal with low supply constraint of sub-1-V operation. The cascade of resonators with distributed feedforward (CRFF) architecture reduces the signal swing of integrators, alleviating the requirement of high slew rate amplifiers at low-power operation. A novel chopper-embedded OTA implemented in the first stage effectively eases the impact of component mismatches and suppresses the 1/f noise. The second and third stages share a single OTA to save the area and power budget. Operated at 0.8-V supply voltage, the proposed modulator achieves 80.3 dB peak SNDR with a 3 kHz sinusoid input over a signal bandwidth of 10 kHz with an OSR of 128 at sampling frequency of 2.56 MHz and a power dissipation of 54 μW. The resulted Figure-of-Merits (FoMs) are 299 fJ/step and 319 fJ/ step at 0.7-V and 0.8-V supply respectively. © 2012 IEEE.