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A 0.8V 64x64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications
Conference paper

A 0.8V 64x64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina applications

Chih-Lin Lee and Chih-Cheng Hsieh
2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, pp.193-196
2011

Abstract

A 0.8V 64x64 CMOS Image Sensor (CIS) array with integrated sense-and-stimulus (SAS) pixel is presented in this paper. The in-pixel photon-to-biphasic-current converter (sense) and balanced current-mode stimulator (stimulus) are proposed to achieve a high integration and low power solution for high-resolution vision recovery. Two operation modes as programming (PG) mode and implanted (IP) mode are integrated in this design for multiple purposes. In PG mode, the output pattern of current stimulator array is programmable with external addresses for patterned electrical stimulus experiments of retina. In IP mode, the chip is fully functional with minimized number of I/O as 4 optimized for implant operation. A 64x64 SAS pixel array with 30x30 um 2 pixel size has been designed and fabricated in TSMC 0.18um CIS technology. Measurement results show a 0.01uA/lux conversion gain and the maximum driving capability of biphasic neural stimulation current pulse is 10μA with a 10kΩ electrode model. It achieves the highest array resolution as 4096 pixels operated at 0.8V, 19.5fps, and 9.6mW. © 2011 IEEE.

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