Abstract
This paper presents an energy-efficient charge-sharing SAR ADC design that targets for 1-V, 8-bit 40MS/s performance. By reconfiguring the networks for the input sampling and the reference banks, the settling time at input sample-hold stage and the pre-charge energy for each evaluation phase can be alleviated, that is equivalent to power saving. In addition, a dedicated asynchronous controller is developed to precisely control the energy for each logic operation. With a 90nm CMOS process, the prototype achieves 113μW (20fJ/conv), 48.4 dB SNDR. Digital controller only dissipates 12.4% of system power. © 2011 JSAP (Japan Society of Applied Physi.