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A 1-V fully differential amplifier with buffered nested-miller compensation
Conference paper

A 1-V fully differential amplifier with buffered nested-miller compensation

Meng-Hung Shen, Po-Min Wang, Li-Wen Wang and Po-Chiun Huang
2009 International SoC Design Conference, ISOCC 2009, pp.309-312
2009

Abstract

Frequency compensation Low voltage Multi-stage amplifier
This paper presents a 1-V three-stage fully differential amplifier with buffered nested-Miller compensation. A transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero. In addition, a feedforward transconductance is used to enhance output large signal response. Using a standard 0.35-μm CMOS technology, measurement results demonstrate that DC gain greater than 90dB, gain-bandwidth product of 4.57MHz, and phase margin of 55° is achieved with 100pF output loads. The settling time for a 1-V pp step is 2μs. All the circuits dissipate 110μW under a single 1-V power supply. ©2009 IEEE.

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