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A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS
Conference paper

A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOS

Kwuang-Han Chang and Chih-Cheng Hsieh
2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings, pp.157-160
02/2017
DOI: https://doi.org/10.1109/ASSCC.2016.7844159

Abstract

redundancy SAR ADC sub-radix and multi-bit-per-cycle Electrical and Electronic Engineering Hardware and Architecture
This paper presents a 0.9 V 1.5 mW 150 MS/s 12-bit SAR ADC in 40 nm CMOS with adaptive radix DAC, which achieves a synergistic integration of multi-bit-per-cycle and subradix techniques with adaptive error-tolerant redundancies. Alternative-reference-switching (ARS) DAC and adaptive-noise-reduction (ANR) comparator are developed to reduce the DAC effective switching capacitance by 47.4% and comparator power by 37.3%. The achieved peak SNDR, SFDR, and FoM are 61.7 dB, 74.4 dB and 10.3 fJ/conversion-step, respectively.

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