Abstract
This paper presents a 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with reference voltage ripple suppression (RVRS) for wireless-powered implantable applications. Using two extra reference capacitive DACs and multiplexed four-input comparator, the reference voltage ripple on main DAC is mimicked and cancelled out during the conversion. By applying the RVRS technique with 2-bit ripple mimicking, the impact from unstable reference is effectively suppressed to be 1/4 (suppression ratio = 4) to release the reference voltage regulation requirement by 4 times and reduce power. The prototyped ADC was fabricated in 90nm CMOS technology with a core area of 0.088mm 2 . At 1V supply voltage and 3MS/s sampling rate, the implemented ADC achieves a SNDR of 62.69 dB with a corresponding ENOB of 10.12 bits. The resulting figure-of-merit (FoM) is 11.6 fJ/conversion-step.