A 12-stage Linear CMOS image sensor with APST-based Time Delay Integration

Conference paper

Jui-Hsin Chang, Chin-Fong Chiu and Chih-Cheng Hsieh

2014 VLSI Design/CAD Symposium

2014

Abstract

CMOS;image sensor;APST

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Title: A 12-stage Linear CMOS image sensor with APST-based Time Delay Integration
Creators - without role: Jui-Hsin Chang
Chin-Fong Chiu
Chih-Cheng Hsieh - 國立清華大學電機資訊學院電機工程學系
Publication Details: 2014 VLSI Design/CAD Symposium
Identifiers: 9957767207006774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper