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A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput
Conference paper

A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput

Hiroshi Nakamura, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, …
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, (SUPPL.), pp.82-83+411
2002

Abstract

Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
A 125 mm 2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm 2 . Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

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