Abstract
This paper presents a 12-bit hybrid successive approximation register (SAR) analog-to-digital converter (ADC) composed of common-mode based switching procedure and time-to-digital converter (TDC). For high-resolution requirement, several issues including the signal-dependent coupling in bootstrapped sample-and-hold circuit and parasitic loading effect of voltage-to-time converter are addressed by proposed design schemes. TDC implemented in oscillation-type adjustable delay cell is proposed with smaller area. Calibration circuit is also implemented to compensate inter-stage offset mismatch and least-significant-bit level alignment. The prototype fabricated in TSMC 0.18μm CMOS technology achieves an effective number of bit (ENOB) of 10.5 bits at 1.2-V supply, 1MS/s, and 11.16μW, resulting in a figure of merit (FOM) of 7.65 fJ/conversion-step.