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A 1.2V fully differential amplifier with buffered reverse nested miller and feedforward compensations
Conference paper

A 1.2V fully differential amplifier with buffered reverse nested miller and feedforward compensations

Meng-Hung Shen, Li-Han Hung and Po-Chiun Huang
2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, pp.171-174
2006

Abstract

This paper presents a low voltage CMOS fully differential operational amplifier. It comprises three gain stages with two compensation schemes, buffered reverse nested Miller compensation (B-RNMC) and feedforward transconductance compensation (FFTC). In B-RNMC, a transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero which may degrade phase margin. In FFTC, a feedforward transconductance helps to enhance output large signal response. Using standard 0.35-μm CMOS technology, measurement results demonstrate that DC gain greater than 90dB, gainbandwidth product of 8.9MHz, and phase margin of 86° is achieved with l00pF output loads. The settling time for a 1.2V pp step is 2.4μs. All the circuits dissipate 342μW under a single 1.2V power supply. © 2006 IEEE.

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