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A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC
Conference paper

A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC

Kwuang-Han Chang and Chih-Cheng Hsieh
2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016, 7482524
31/05/2016
DOI: https://doi.org/10.1109/VLSI-DAT.2016.7482524

Abstract

Capacitor mismatch Digital calibration LMS Redundancy SAR ADC
This paper presents a 12b SAR ADC with segmented sub-radix-2 DAC and embedded digital calibration. The dither-based calibration with LMS adaptive filter is implemented to track the optimum bit-weights for compensation of DAC mismatch. Mid-threshold comparison switching procedure is proposed to tolerate both-side settling error by equalizing the up and down DAC transition voltage during SAR conversion. The prototyped SAR ADC achieves an FoM of 18.9fJ/conversion-step at 10MS/s and 1V supply. The ADC core and digital calibration part occupies an area of 0.05mm 2 and 0.04mm 2 in 90nm CMOS, respectively.

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