Abstract
A 1.5V(A)/0.8V(D) high dynamic range (HDR) readout integrated circuit (ROIC) with tunable sensitive range and fixed pattern noise (FPN) reduction for infrared focal plane arrays (IR FPAs) is presented. A pulse width modulation (PWM) readout with capacitive trans-impedance amplifier (CTIA) front end, dual-exposure extended-counting (DEEC) [1], and aligned time-control ramp (ATCR) generator are developed for dynamic range boost. Auto-zeroing and offset cancellation (AZOC) mechanisms are implemented to reduce readout noise and FPN. The digital supply voltage of logic part is decreased to 0.8V for power reduction. The ROIC prototype with an embedded test CMOS image sensor array of 64×64 and 15?m×15?m pixel pitch has been designed and fabricated in 0.18?m CMOS technology. The experimental results show an achieved high dynamic range of 132dB, a FPN in dark of 0.02%, a frame rate of 230fps, and an iFOM of 1.27 nW/frame.pix at 1.5V(A)/0.8V(D) operation.