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A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology
Conference paper

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark Ferriss, Herschel Ainspan, Alexander Rylyakov, …
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, 6945983
04/11/2014
DOI: https://doi.org/10.1109/CICC.2014.6945983

Abstract

A power-scalable 2-Byte I/O operating at 12-Gb/s per lane is reported. The I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels. Measurements of a test chip fabricated in 32nm SOI CMOS technology demonstrate 1.4-pJ/b efficiency over 0.75' Megtron-6 PCB traces, and 1.9-pJ/b efficiency over 20' Megtron-6 PCB traces. © 2014 IEEE.

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