A 17.4fJ/c-s 0.9V 10-bit 1MS/s Low-Power Asynchronous Successive Approximation Register Analog to Digital Converter

Conference paper

Hsin-Yuan Huang, Pei-Chen Lee, Chi-Hui Chen, Yi-Ting Tseng and Chih-Cheng Hsieh

2012 VLSI Design/CAD Symposium

2012

Abstract

Successive Approximation Register;Analog to Digital Converter

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Title: A 17.4fJ/c-s 0.9V 10-bit 1MS/s Low-Power Asynchronous Successive Approximation Register Analog to Digital Converter
Creators - without role: Hsin-Yuan Huang
Pei-Chen Lee
Chi-Hui Chen
Yi-Ting Tseng
Chih-Cheng Hsieh - 國立清華大學電機資訊學院電機工程學系
Publication Details: 2012 VLSI Design/CAD Symposium
Identifiers: 9957776256606774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: Traditional Chinese
Resource Type: Conference paper