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A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization
Conference paper

A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization

Liao-Chuan Chen, Zhaofang Li, Yi-Jhen Lin, Kuan-Pei Lee and Kea-Tiong Tang
APCCAS 2022 - 2022 IEEE Asia Pacific Conference on Circuits and Systems, pp.15-19
2022
DOI: https://doi.org/10.1109/APCCAS55924.2022.10090334

Abstract

accelerator convolutional neural network (CNN) data movement energy efficiency Hardware and Architecture Electrical and Electronic Engineering Artificial Intelligence Computer Science Applications
Deep convolutional neural networks feature numerous parameters, causing data movement to usually dominate the power consumed when computing inferences. This paper proposes an on-chip buffer access optimization method and high-data-reuse architecture that can reduce the power consumed by an on-chip buffer by up to 67.8%. The chip is designed in a TSMC 40 nm process running at 200 MHz and achieves energy efficiency of 1.93 TOPS/W.

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