Logo image
Back
A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency
Conference paper

A 210mV 7.3MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency

Chien-Fu Chen, Ting-Hao Chang, Lai-Fu Chen, Meng-Fan Chang and Hiroyuki Yamauchi
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp.C130-C131
2013

Abstract

Electrical and Electronic Engineering,Electronic Optical and Magnetic Materials
This work proposes an 8T cell with dual data-aware write-assist (D2AW) and negative read-WL (NRWL) schemes to increase the figure of merit (FOM): [cell stability (CS)*cycle frequency (f)]/[cell area (A)*minimum VDD (VDDmin)]. The column-based D2AW provides, for the first time, the solution to the trade-off between the row/column half-select (HS)-CS margins and the write margin (WM) thanks to the dual data-aware controls of: 1) cell-VSS (DA-CVSS) and 2) write-wordline (DA-WWL). NRWL expands the RBL voltage swing (V RBLS ), while accelerating BL developing time (T BLS ). A fabricated 65nm 128-row 16Kb D 2 AW8T SRAM achieved 7.3MHz/48MHz at VDD=210mV/300mV. The resulting 'CS*f/(A*VDDmin)' is 14+x higher than that of other low-VDDmin SRAM cells. © 2013 JSAP.

Metrics

1 Record Views

Details

Logo image