A 2.16pJ/b 112Gb/s PAM-4 transceiver with time-interleaved 2b/3b ADCs and unbalanced baud-rate CDR for XSR applications in 28nm CMOS

Conference paper

2024 IEEE International Solid-State Circuits Conference (ISSCC)

02/2024

Abstract

wireline;PAM-4;time-interleaved ADC;unbalanced CDR

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Title: A 2.16pJ/b 112Gb/s PAM-4 transceiver with time-interleaved 2b/3b ADCs and unbalanced baud-rate CDR for XSR applications in 28nm CMOS
Creators - without role: 秉璇謝
Publication Details: 2024 IEEE International Solid-State Circuits Conference (ISSCC)
Identifiers: 9957769875606774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper