Abstract
Battery-powered tiny-AI edge devices require large-capacity nonvolatile compute-in-memory (nvCIM), with multibit input (IN), weight (W), and output (OUT) precision to support complex applications, high-energy efficiency (EF_{{mathrm {MAC}}}), and short computing latency (t_{{mathrm {AC}}}) for multiply-and-accumulate (MAC) operations. Due to the low read-disturbfree voltage of nonvolatile memory (NVM) devices and the large parasitic load on the bitline, most existing Mb-level nvCIM macros use a current-mode read scheme [1-5] and only achieve a low IN-W precision (binary to 4b).