Abstract
A NAND structure memory cell with 2.2 × 1.05 μm 2 size per bit, based on a 0.6 μm design rule, has been developed for 16 Mb flash EEPROMs. The cell size is about 64% of the smallest 16 Mb EPROM cell so far reported. An extremely small cell can be realized by the following technologies: (1) newly developed 0.3 μm space self-aligned stacked gate patterning, (2) a NAND structured cell array which contains 16 memory transistors in series, and (3) high-voltage field isolation technology used to isolate neighboring bits. The first and second technologies reduce the length of the cell by 67.6% compared with the conventional NAND structured cell using the same design rule, while the third technology reduces the width by 84.6%.