Abstract
Applications of wireless sensor networks and biomedical devices frequently require an ADC with medium resolution (8 to 12b) running at hundreds of kS/s to a few MS/s. Successive-approximation register (SAR) ADCs show convincing performance with inherent low-power operation and high efficiency. DAC switching energy and SAR control logic are the main power-hungry blocks in ADC designs, and this attracts much research interest [1-6]. Set-and-down [1-3], step-wise [4], merged capacitor [5], and input-range-prediction [6] show improved switching-energy efficiency with design penalties such as common-mode shift, extra auxiliary capacitors, extra voltage reference (Vcm), and an extra conversion step, respectively. Reducing power with a smaller unit capacitance requires extra calibration to meet accuracy requirements [2-3]. Without the aforementioned drawbacks, this work presents a SAR ADC with FoM performance as low as 2.4fJ/conv-step, and a variable sampling rate optimized by adequately scaling the supply. © 2013 IEEE.