Abstract
In this paper, a first 3.2Gb/s 20:1 CML transmitter was developed for integrating with 8/10B encoders in high speed network applications. Compared with the common 10:1 multiplexer, this 20:1 transmitter reduces the required operating frequency in routers and switches by half. A double phase source coupled logic based differential circuit is used to achieve the 20:1 serailziation with reduced noise effects. A low-power PLL is embedded for generating on chip dual phase clocks. A wide-band low power high speed CML output buffer provides 250mV output voltage swing at 10Gb/s. The overall chip size is 650μm × 950μm with power consumption of 104 mW at 1.6GHz.