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A 40Ms/s 12-bit zero-crossing based SAR-assisted two-stage pipelined ADC with adaptive level shifting
Conference paper

A 40Ms/s 12-bit zero-crossing based SAR-assisted two-stage pipelined ADC with adaptive level shifting

Yung-Te Chang, Min-Rui Wu and Chih-Cheng Hsieh
Proceedings - IEEE International Symposium on Circuits and Systems, Vol.2019-May, 8702449
2019
DOI: https://doi.org/10.1109/ISCAS.2019.8702449

Abstract

Pipelined SAR ADC SAR-assisted pipelined ADC ZCBC Zero-crossing Electrical and Electronic Engineering
This paper presents a power-efficient 12-bit zero-crossing based (ZBC) successive-approximation register (SAR)assisted two-stage pipeline analog-to-digital converter (ADC). The ZBC's error propagation of conventional multiple stage pipeline ADC is solved by using the proposed two-stage pipelined architecture with one residue amplification only. Moreover, to avoid the signal polarity dependent overshoot error of ZCB amplification, the adaptive level shifting (ALS) scheme is proposed to provide a constant polarity with a x3 charge transfer speed improvement compared to the conventional approach. The prototyped ADC is fabricated in 40nm CMOS technology with core area of 0.019mm 2 . At 0.9V supply voltage and 40MS/s Sampling rate with 1MHZ input, the implemented ADC achieves a SNDR of 62.2dB with corresponding ENOB of 10.04 bits. The resulting figure-of-merit (FoM) is 5.6fJ/conversion-step.

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