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A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A system
Conference paper

A 516Mb/s 0.2nJ/bit/iter variable-block-size turbo decoder for 3GPP LTE-A system

Chi-Hsuan Hsieh, Ming-Yong Lee and Yuan-Hao Huang
ISOCC 2012 - 2012 International SoC Design Conference, pp.343-346
2012

Abstract

This paper presents a high-throughput turbo decoder supporting 188 block sizes for 3GPP LTE-Advanced system. This study investigates the memory contention problem when the turbo decoder has none-power-of-two degree of parallelism of MAP processors. The proposed method aims to reduce unnecessary MAP processors when 2 n MAP processors costs too much for a targeted throughput rate. The turbo decoder achieves a throughput of 516Mb/s for 6144-bit block after 4 iterations with 0.2nJ/bit/iteration energy efficiency using a 90nm CMOS technology. © 2012 IEEE.

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