A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS

Pen-Jui Peng; Jeng-Feng Li; Li-Yang Chen; Jri Lee

doi:10.1109/ISSCC.2017.7870285

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Conference paper

A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS

Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen and Jri Lee

Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.60, pp.110-111

03/2017

DOI: https://doi.org/10.1109/ISSCC.2017.7870285

Abstract

Electronic

Optical and Magnetic Materials

Electrical and Electronic Engineering

Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/deserializer, FFE/CTLE/DFE, CDR, and eye-monitoring circuits. It achieves BER<10 <sup>-12</sup> under 24dB loss at 14GHz while dissipating 602mW of power.

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Title: A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS
Translated title: A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS
Creators - without role: Pen-Jui Peng - National Taiwan University
Jeng-Feng Li - National Taiwan University
Li-Yang Chen - National Taiwan University
Jri Lee - National Taiwan University
Publication Details: Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Vol.60, pp.110-111
Identifiers: 9781509037575; 9957775809906774
Academic Unit: Department of Electrical Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Conference paper

A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS

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