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A 62.45 TOPS/W Spike-Based Convolution Neural Network Accelerator with Spatiotemporal Parallel Data Flow and Sparsity Mechanism
Conference paper

A 62.45 TOPS/W Spike-Based Convolution Neural Network Accelerator with Spatiotemporal Parallel Data Flow and Sparsity Mechanism

Chen-Han Hsu, Yu-Hsiang Cheng, Zhaofang Li, Ping-Li Huang and Kea-Tiong Tang
Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, pp.182-185
2022

Abstract

accelerator area efficiency energy efficiency sparsity Spiking neural network Artificial Intelligence Computer Science Applications Computer Vision and Pattern Recognition Hardware and Architecture Human-Computer Interaction Electrical and Electronic Engineering
Convolutional neural networks (CNNs) have been widely used for image recognition and classification in recent years. Low energy consumption is crucial in the circuit design of edge devices, and data reuse is one method of reducing energy consumption. In addition, spiking neural networks (SNNs) are receiving increasing attention due to their low power use. However, the temporal characteristic of SNNs causes repeated data access at different time steps, leading to high energy consumption. In this paper, a spiked-based CNN accelerator that can support various inference time steps and models is proposed. Spatiotemporal parallel data flows are employed to reuse data from different time steps and, convolution operations are used to reduce energy consumption. Furthermore, the accelerator is designed for high sparsity and event driven SNNs. The synthesis achieves power efficiency of 62.45 TOPS/W and area efficiency of 7.58 TOPS/kmm2.

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