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A 65nm Node Strained SOI Technology with Slim Spacer
Conference paper

A 65nm Node Strained SOI Technology with Slim Spacer

Fu-Liang Yang, Chien-Chao Huang, Hou-Yu Chen, Jhon-Jhy Liaw, Tang-Xuan Chung, Hung-Wei Chen, Chang-Yun Chang, Cheng-Chuan Huang, Kuang-Hsin Chen, Di-Hong Lee, …
Technical Digest - International Electron Devices Meeting, pp.627-630
2003
Appears in  keyword about Physics

Abstract

Electronic Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering Materials Chemistry
A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 μA/μm for N-FET and P-FET, respectively, at an off-state leakage of 40 nA/μm using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce 10-20% layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15% higher inverter speed compared to planar SOI devices at the same drive current.

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