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A CMOS-compatible, neuro-transistor array with monolithically-integrated circuit for studying cultured neuronal networks
Conference paper

A CMOS-compatible, neuro-transistor array with monolithically-integrated circuit for studying cultured neuronal networks

Hsiang-Chiu Wu, Sheng-Jen Chang and Hsin Chen
2012 IEEE 10th International New Circuits and Systems Conference, NEWCAS 2012, pp.305-308
2012

Abstract

In-plan microelectrode arrays have been proven to be useful tools for studying the connection and functions of neural tissues. But the number of electrodes is limited by the complex integration between sensors and signal-processing circuits. This paper presents a single-chip neural-electronic interface integrating the oxide-semiconductor filed effect transistors (OSFETs) with the signal-processing circuits. The chip is fabricated in the standard TSMC 0.35μm process, and then by die-level CMOS post process. © 2012 IEEE.

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