Logo image
A CMOS imaging platform using single photon avalanche diode array in standard technology
Conference paper

A CMOS imaging platform using single photon avalanche diode array in standard technology

Tzu-Hsiang Hsu and Chih-Cheng Hsieh
Proceedings of IEEE Sensors, Vol.2017-December, pp.1-3
12/2017

Abstract

CMOS image sensor column parallel readout circuit single-photon avalanche diode (SPAD) Electrical and Electronic Engineering
A compact single-photon avalanche diode (SPAD) testing array fabricated in standard 0.18μm CMOS technology is presented. Four types of SPAD are designed in 18μm pixel pitch with 3μm active region and arranged in four 16×30 sub-arrays. The implemented column readout circuit consists of column-shared comparator and tunable hold-off time control circuit, which performs the avalanche sensing with feedback loop to achieve the active recharge operation without complex in-pixel circuitry. With the implemented active feedback path for SPAD reset operation, the maximum count rate is improved with reduced after-pulsing probability (APP). By means of the proposed architecture, the statistical performance of dark count rate (DCR), photon detection efficiency (PDE), and photon response are presented and discussed. The SPAD-based imaging platform successfully demonstrates captured images with photon shot-noise-limited performance.

Metrics

1 Record Views

Details

Logo image