摘要
A calibration-free 13-bit 10-MS/s full-analog SAR ADC integrates the functions of comparator, SAR logic, and DAC switches into multiple inverter-based regenerative amplifiers (IRAs) to have a double timing budget for settling and relax the bandwidth requirement of analog circuits compared to the conventional SAR ADC. The continuous-time feedforward cascaded (CTFC) Op-amps are proposed to enhance the residue SNR using open-loop low gain-bandwidth amplifiers instead of closed-loop high-precision amplifiers. The prototype in 40nm CMOS occupies 0.013 mm 2 and achieves 67.6 dB SNDR 77.2 dB SFDR 3.2 fJ/conv.-step FoMw, and 176.6 dB FoMs without any calibration.