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A Dynamic Expansion Order Algorithm for the SAT-based Minimization
Conference paper

A Dynamic Expansion Order Algorithm for the SAT-based Minimization

Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen and Chun- Yao Wang
International System on Chip Conference, Vol.2020-September, pp.271-276
09/2020
DOI: https://doi.org/10.1109/SOCC49529.2020.9524758

Abstract

Digital circuit High dimension Boolean space Logic optimization SAT problem Hardware and Architecture Control and Systems Engineering Electrical and Electronic Engineering
Logic minimization attracted much attention in the early days because it is the engine for logic synthesis and optimization. Recently, a previous work proposed a SAT-based minimization algorithm for the patch function in the Engineering Change Order (ECO) problem. However, the algorithm is time-consuming for the functions in high dimension Boolean space. Therefore, in this paper, we propose an efficient algorithm that is suitable for the functions in high dimension Boolean space.

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