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A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation
Conference paper

A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation

Hsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen and Chun-Yao Wang
Proceedings - International Symposium on Quality Electronic Design, ISQED, Vol.2023-April
2023

Abstract

cluster tool simulation wafer transferring system Hardware and Architecture Electrical and Electronic Engineering Safety Risk Reliability and Quality
The semiconductor manufacturing process consists of multiple steps and is usually time-consuming. Information like the turnaround time of a certain batch of wafers can be very useful for manufacturing engineers. A simulation model of manufacturing process can help predict the performance of manufacturing process efficiently, which is very beneficial to the manufacturing engineers. The simulation result can also deliver messages to system engineers for achieving better throughput after adjustment. In this work, we propose a flexible simulation framework for a cluster tool. We implemented the simulator in C++ language with SystemC. The batch information used for the design of simulator was gathered from industrial data. The experimental results show that there is only less than 2% difference between the simulation and the manufacturing data in terms of entire processing time, which indicates the high accuracy of the simulator. The experimental results with the proposed dispatching method achieve a higher throughput compared to the manufacturing data such that the dispatching time points can be recommended to the system engineers.

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