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A Hardware-Realizable Framework for Time Stamp Scheduling Discipline in High Speed Networks
Conference paper

A Hardware-Realizable Framework for Time Stamp Scheduling Discipline in High Speed Networks

Y.-C. Wang and C.-C. Lu
2001 International Symposium on Communications
2001

Abstract

Time Stamp;Quality Of Service;Scheduling Algorithm;Hardware Realizable Framework;High Speed Network
A scheduling algorithm in high speed network should be smart enough toguarantee quality-of-service (Qos), but it must also have a simpleimplementation so that packets can be processed at the speed of thetransmission link. The technique of time stamp scheduling algorithmhas been proposed, but the complexity of this technique prevents theiruse in elements of high speed networks that must select a packet fortransmission every few microseconds. This paper presents a frameworkfor time stamp scheduling algorithm amenable to efficient hardwareimplementation in elements of high speed networks. In order toillustrate the advantage for this framework, the application forimplementing Self Clocked Fair Queueing (SCFQ) is presented becausethey satisfy the design criterion of efficiency, flexibility, protection.

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