Abstract
We study in this paper the floorplan design problem under the practical assumptions that the width and height of the chip are fixed, and that each soft block is rectangular and is associated with only the total area of the cells contained in it (and hence the number of shape curves is infinite). We present a routability-driven floorplanner which measures chip routability in terms of the utilization of each soft block. Based on this idea, the floorplanner is designed by using the simulated annealing and binary search techniques. The preliminary experimental results are provided to demonstrate the effectiveness of the new floorplanner.