摘要
Low-power Al edge devices should provide short-latency (\mathsf{T}_{\mathsf{WK-RP}}) and low-energy (\mathsf{E}_{\mathsf{WK-RP}}) wakeup responses from power-off mode to handle event-triggered computing tasks with high inference accuracy (IA), which requires high-capacity nonvolatile memory (NVM) to store high-precision weight data in power-off and high bit-precision multiply and accumulate (MAC) operations with high energy efficiency. SRAM computing-in-memory (CIM) and digital processors suffer large \mathsf{E}_{\mathsf{WK-RP}} and long \mathsf{T}_{\mathsf{WK-RP}} due to the movement of weight data from off-chip NVM to the on-chip buffer and processing unit after wakeup. Thus, on-chip nonvolatile CIM (nvCIM) is preferred for Al-edge processors by combining NVM storage and computing tasks on the same macro. Among nvCIM structures, in-memory compute (IMC) [1] provides short computing latency and high energy efficiency, but suffers from low computing yield. Near-memory compute (NMC) [2-4] provides high computing yield, but suffers long computing latency and low energy efficiency.