Abstract
We propose a software tool for automatic generation of hardware accelerators for performing Discrete Wavelet Transform (DWT) with user-specified coefficient parameters. In addition to (5, 3) and (9, 7) DWT filters adopted by the next generation JPEG2000 image compression standard, other useful filters such as (9, 3), (6, 10), and (2, 2) can also be generated. The generated hardware IPs can perform both forward and inverse tansform (FDWT and IDWT). We analyze variable life time for register allocation with low power consumption and apply register retiming technology to improve circuit performance. Our tool also produces on-chip-bus interface circuit compliant with the AMBA protocol together with associated device driver so that the generated IPs is ready for SOC integration. We verify the proposed approach by integrating generated IPs into an SOC platform running JPEG2000 application software. Experimental results demonstrated that the proposed approach is indeed effective in enhancing the productivity of hardware accelerator IP design