Abstract
As the manufacturing technology keeps shrinking, the number of I/O pins in a modern VLSI chip has easily grown to hundreds, or even thousands. With the pressing need of connecting the huge number of I/O pins to a PCB (Printed Circuit Board), a BGA (Ball Grid Array) package is used mostly nowadays. In this paper, we present a two-layer BGA global routing algorithm which routes nets one at a time while considering the minimization of the total wirelength and overflow. The experimental results show that our algorithm averagely decreases 96.8% total overflow and 83.33% maximum overflow as compared to a recent work; besides, our algorithm produces smaller total wirelength and runs 4.39 times faster.