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A VLIW-based post compilation framework for multimedia embedded DSPs with hardware specific optimizations
Conference paper   Peer reviewed

A VLIW-based post compilation framework for multimedia embedded DSPs with hardware specific optimizations

Meng-Hsuan Cheng, Kenn Slagter, Tai-Wen Lung and YEH-CHING CHUNG
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol.6083 LNCS, pp.51-58
2010

Abstract

DSP Compiler optimization Post optimization VLIW Compiler optimization
In high performance and low power multimedia embedded system design, VLIW-based embedded DSPs compilers that exploit ILP have become popular and play an important role today. For this reason, we need optimizing embedded DSP compilers that can both generate capable and efficient code in terms of performance, power, size, and productivity. In this paper, we show a post-compilation framework that can further optimize programs that have already been compiled and optimized by another compiler, by using runtime information and exploiting hardware specific features of DSPs. Finally, we show in our simulation results, that even programs compiled at the best optimization level, can obtain significant improvement through the use of this framework. © 2010 Springer-Verlag.

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